VDD = 2.5V±5% , VDDQ = 2.5V±5%
•  SSTL_2 compatible inputs/outputs
•  4 banks operation
•  MRS cycle with address key programs
     -. CAS  latency 2,3 (clock)
     -. Burst length (2, 4, 8 and Full page)
     -. Burst type (sequential & interleave)
•  Full page burst length for sequential burst type only
•  Start address of the full page burst should be even
•  All inputs except data & DM are sampled at the rising edge of the system clock
•  Differential clock input (CK & /CK)
•  Data I/O transaction on both edges of Data strobe
•  4 DQS (1 DQS/Byte)
•  DLL aligns DQ and DQS transaction with Clock transaction
•  Edge aligned data & data strobe output
•  DM for write masking only
•  Auto & self refresh 
•  32ms refresh period (4K cycle)
•  144-Ball FBGA package
•  Maximum clock frequency up to 200MHz
•  Maximum data rate up to 400Mbps/pin