• JEDEC standard 1.8V and 2.5V power supply.
• Four internal banks for concurrent operation
• MRS cycle with address key programs
     - CAS  latency 2, 3 (clock)
     - Burst length (2, 4, 8, 16)
     - Burst type (sequential & interleave)
• Fully differential clock inputs (CK, /CK)
• All inputs except data & DM are sampled at the rising edge of the system clock
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data (DQS)
• DM for write masking only
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• 64ms refresh period (4K cycle)
• Auto & self refresh 
• Concurrent Auto Precharge
• Maximum clock frequency up to 166MHZ
• Maximum data rate up to 333Mbps/pin
• Special Power Saving supports.
     - PASR (Partial Array Self Refresh)
     - Auto TCSR (Temperature Compensated Self Refresh)
     - Deep Power Down Mode
     - Programmable Driver Strength Control by Full Strength or 1/2, 1/4, 1/8 of Full Strength
• LVCMOS compatible inputs/outputs